/*
    IOHal.h, Copyright (c) by Silvio Dragone & David Reist,
    Swiss Federal Institute of Technology,
    Computer Engineering and Networks Laboratory.
 
    TOPSY -- A Teachable Operating System.
             Implementation of a tiny and simple
             micro kernel for teaching purposes.
 
    For further information, please visit http://www.tik.ee.ethz.ch/~topsy
 
    This software is provided under the terms of the GNU General Public Licence.
 
    A full copy of the GNU GPL is provided in the file COPYING found in the
    development root of Topsy.
*/

#ifndef _IOHAL_H_
# define _IOHAL_H_

# include "Configuration.h"
# include "cpu.h"

//# define CONSOLE_BASE UART_A_BASE
# define MAXPUTSTRINGLEN 320
/* IXP2400 UART_RBR Register */ /* DLAB == 0 */
/* Receive Buffer Register */
# define UART_RBR_REGISTER    0xC0030000

/* IXP2400 UART_THR Register */ /* DLAB == 0 */
/* Transmit Holding Register */
# define UART_THR_REGISTER    0xC0030000

/* IXP2400 UART_DLRL Register */ /* DLAB == 1 */
/* Low Byte baud control register */
# define UART_DLRL_REGISTER  0xC0030000

/* IXP2400 UART_DLRH Register */ /* DLAB == 1 */
/* High Byte baud control register */
# define UART_DLRH_REGISTER   0xC0030004

/* IXP2400 UART_IER Register */ /* DLAB == 0 */
/* Interrupt Enable Register */
# define UART_IER_REGISTER     0xC0030004   /* register address */
# define IER_RAVIE_YES         0x1          /* enable receiver interrupt */
# define IER_RLSE_YES          0x4
# define IER_UUE_YES           0x40         /* enable UART unit */

/* IXP2400 UART_IIR Register */
/* Interrupt Identification Register */
# define UART_IIR_REGISTER     0xC0030008
# define IIR_RDA               0x4          /* received data available */

/* IXP2400 UART_FCR Register */
/* Fifo Control Register */
# define UART_FCR_REGISTER     0xC0030008

/* IXP2400 UART_LCR Register */
/* Line Control Register */
# define UART_LCR_REGISTER     0xC003000C   /* UART_LCR register address */
# define LCR_WLS_8BIT          0x3          /* Wordlength-selector to 8 bit */
# define LCR_STB_2BIT          0x4          /* Set 2 Stop-bits. negate: 1 Stop-bit */
# define LCR_PEN_YES           0x8          /* Enable Parity-check */
//#define LCR_EPS_YES           0x1          /* Set even parity */
//#define LCR_STKYP
//#define LCR_SB
# define LCR_DLAB              0x80         /* Set DLAB bit (needed for setting baud rate) */

/* IXP2400 UART_LSR Register */
/* Line Status Register */
# define UART_LSR_REGISTER     0xC0030014
# define LSR_TDRQ              0x20         /* Allowed to write to THR */

/* IXP2400 UART_SPR Register */
/* Scratch Pad Register */
# define UART_SPR_REGISTER     0xC003001C

/* those two contain hardware driver code */
void ioConsoleInit(void);
void ioConsolePutChar(char c);

/* SA1100 UART_CR Register */
/* not ixp2400-ready! */
#define TRANSMIT_BREAK         0x1     /* 1: assert TXD pin low */
#define PARITY_ENABLE          0x2     /* 0: no parity, 1: parity */
#define PARITY_SELECT          0x4     /* 0: even, 1: odd */
#define STOP_BIT_SELECT        0x8     /* 0: 1 stop bit, 1: 2 stop bit */
#define RX_INTERRUPT_ENABLE    0x10    /* 0: disabled, 1: enabled (interrupt when Rx FIFO not empty) */
#define DATA_SIZE_SELECT_MASK  0x60    /* bit 6..5 (0x20 | 0x40),

*                                         * 0x0:
5 bit
*                                         * 0x1:
6
*                                         * 0x2:
7
*                                         * 0x3:
8     */
#define UART_ENABLE            0x80    /* 0: disabled, 1: enabled */
#define TX_INTERRUPT_ENABLE    0x100   /* 0: disabled, 1: enabled (interrupt when Tx FIFO empty) */
#define UART_INTERRUPT_SELECT  0x200   /* 0: IRQ, 1: FIQ */
#define BAUD_RATE_DIVISOR_MASK 0x3FF0000 /* bit 25..16 (10 bit),
*                                           * 0x2FF:
300 BAUD
*                                           * 0xBF:
1200
*                                           * 0x5F:
2400
*                                           * 0x2F:
4800
*                                           * 0x17:
9600
*                                           * 0xB:
19200
*                                           * 0x5:
38400
*                                           * 0x3:
57600
*                                           * 0x1:
115200
*                                           * 0x0:
230400      */

/* SA1100 UART_DR Register */
#define UART_DATA_MASK         0xFF  /* bit 7..0,
*                                     * read:
read data from Rx FIFO,
*                                     * write:
write data to Tx FIFO */
#define DR_PARITY_ERROR        0x100 /* 1: a parity error occurred */
#define DR_FRAMING_ERROR       0x200 /* 1: a framing error occurred */
#define RX_OVERFLOW            0x400 /* 1: a Rx overrun occurred, data following to current was lost */

//#define UART_DR_REGISTER       0x90003C00 /* UART_DR register address */


#define IXP2400_UART_BUFSIZE    64      /* size taken from hrm */
#define UART_REGISTER_SET_SIZE 0x20   /* size for one channel */

//#define CONSOLE_BASE           UART_A_BASE

#endif
