/*
    tlb.S, Copyright  (c) by Eckart Zitzler,
    Swiss Federal Institute of Technology,
    Computer Engineering and Networks Laboratory.

    TOPSY -- A Teachable Operating System.
             Implementation of a tiny and simple
             micro kernel for teaching purposes.

    For further information, please visit http://www.tik.ee.ethz.ch/~topsy

    This software is provided under the terms of the GNU General Public Licence.

    A full copy of the GNU GPL is provided in the file COPYING found in the 
    development root of Topsy.
*/
/*
	
	File:                  $Source: /home/ruf/cvs_Topsy/cvs/Topsy/Memory/mips/tlb.S,v $
 	Author(s):             Eckart Zitzler
 	Affiliation:           ETH Zuerich, TIK
 	Version:               $Revision: 2922 $
 	Creation Date:         
 	Last Date of Change:   $Date: 2007-03-19 17:48:52 +0100 (Mon, 19 Mär 2007) $      by: $Author: baderma $
	
*/

#include "asm.h"
#include "cpu.h"

	.text
	.align 2

FRAME(setR3kTLBEntry)

	/* mask interrupts, we switch PD and if an INT is caused here
		 we may end in the wrong PD */
	mfc0  k1, C0_STATUS
	srl   k0, k1, 1
	sll   k0, k0, 1
	mtc0  k0, C0_STATUS
	
	mfc0  k0, c0_tlbhi
	mtc0	a0, C0_TLBLO
	mtc0	a1, c0_tlbhi
	sll	a2, a2, TLB_IND_INX_SHIFT_R3k
	mtc0	a2, C0_TLBIND
	tlbwi
	mtc0	k0, c0_tlbhi

	mtc0  k1, C0_STATUS
	
END(setR3kTLBEntry)

FRAME(setR3kHITLBEntry)

	mtc0	a0, c0_tlbhi

END(setR3kHITLBEntry)

FRAME(getR3kHITLBEntry)

	mfc0	v0, c0_tlbhi

END(getR3kHITLBEntry)

FRAME(getR3kLOTLBEntry)

	mfc0	v0, C0_TLBLO

END(getR3kLOTLBEntry)

FRAME(setR3kTLBRandom)

	/* mask interrupts, we switch PD and if an INT is caused here
		 we may end in the wrong PD */
	mfc0  k1, C0_STATUS
	srl   k0, k1, 1
	sll   k0, k0, 1
	mtc0  k0, C0_STATUS
	
	mfc0  k0, c0_tlbhi
	mtc0	a0, C0_TLBLO
	mtc0	a1, c0_tlbhi
	tlbwr
	mtc0	k0, c0_tlbhi

	mtc0  k1, C0_STATUS

END(setR3kTLBRandom)

FRAME(probeR3kTLBEntry)

	/* mask interrupts, we switch PD and if an INT is caused here
		 we may end in the wrong PD */
	mfc0  k1, C0_STATUS
	srl   k0, k1, 1
	sll   k0, k0, 1
	mtc0  k0, C0_STATUS
	
	mfc0	k0, c0_tlbhi
	mtc0	a0, c0_tlbhi
	tlbp
	tlbr
	mfc0  v0, C0_TLBIND
	mtc0	k0, c0_tlbhi

	mtc0  k1, C0_STATUS

END(probeR3kTLBEntry)
	

	
FRAME(setR4kTLBEntry)

	.set	mips3
	
	mtc0	zero, C0_TLBPM
	mtc0	a0, C0_TLBLO0
	mtc0	a1, C0_TLBLO1
	mtc0	a2, c0_tlbhi
	sll	a3, a3, TLB_IND_INX_SHIFT_R4k
	mtc0	a3, C0_TLBIND
	tlbwi
	
	.set	mips0
	
END(setR4kTLBEntry)

FRAME(setR4kTLBWired)

	.set	mips3
	
	mtc0	a0, C0_TLBWRD

	.set	mips0
	
END(setR4kTLBWired)
	
	

