/*
    Copyright 2001 (c) by Authors,
    Swiss Federal Institute of Technology,
    Computer Engineering and Networks Laboratory.
 
    TOPSY -- A Teachable Operating System.
             Implementation of a tiny and simple
             micro kernel for teaching purposes.
 
    For further information, please visit http://www.tik.ee.ethz.ch/~topsy
 
    This software is provided under the terms of the GNU General Public 
    Licence. A full copy of the GNU GPL is provided in the file COPYING 
    found in the development root of Topsy.
*/
/*
  
    File:                  $Source: /home/ruf/cvs_Topsy/cvs/Topsy/IO/sa1100/Drivers/Attic/IXP_Defines.h,v $
    Affiliation:           ETH Zuerich, TIK
    Version:               $Revision: 2922 $
    Last Date of Change:   $Date: 2007-03-19 17:48:52 +0100 (Mon, 19 Mär 2007) $  by: $Author: baderma $
 
*/

// this code is based upon parts of vera from Princeton

/*
**  PROJECT
**      IXP1200 Toolkit
**
**  DESCRIPTION
**      General IXP1200 definitions
**
**  DEVELOPERS
**      Scott C. Karlin   (scott@cs.princeton.edu)
**      Yitzchak Gottlieb (zuki@cs.princeton.edu)
*/

#ifndef _IXP_DEFINES_H_
#define _IXP_DEFINES_H_

/*************************************************************************/

#define IXP1200_SRAM_CSR                      0x38000000   /* Register Address */
#define   IXP1200_SRAM_CSR_RLK                  0x00100000 /*   Read Lock Order  */
#define   IXP1200_SRAM_CSR_8MF                  0x00004000 /*   2 MB x <=4 banks Flash */
#define   IXP1200_SRAM_CSR_2MSR                 0x00000200 /*   2 MB SRAM */
#define IXP1200_SRAM_SLOW_CONFIG              0x38000020   /* Register Address */
#define   IXP1200_SRAM_SLOW_CONFIG_BCC_25       0x00001900 /*   BootROM is 25 cycles */
#define   IXP1200_SRAM_SLOW_CONFIG_SCC_89       0x00000059 /*   Slow Port is 89 cycles */
#define   IXP1200_SRAM_SLOW_CONFIG_SCC_83       0x00000053 /*   Slow Port is 83 cycles */
#define IXP1200_SRAM_BOOT_CONFIG              0x38000024   /* BootROM Config Reg Addr */
#define   IXP1200_SRAM_BOOT_CONFIG_BRWA_24      0x18000000 /*   R/W      Assert = 24 */
#define   IXP1200_SRAM_BOOT_CONFIG_BCEA_24      0x00180000 /*   Enable   Assert = 24 */
#define   IXP1200_SRAM_BOOT_CONFIG_BRWD_4       0x00000400 /*   R/W    Deassert =  4 */
#define   IXP1200_SRAM_BOOT_CONFIG_BCED_0       0x00000000 /*   Enable Deassert =  0 */
#define IXP1200_SRAM_SLOWPORT_CONFIG          0x38000028   /* Slow Port Config Reg Addr */
#define   IXP1200_SRAM_SLOWPORT_CONFIG_SRWA_76  0x4C000000 /*   R/W      Assert = 76 */
#define   IXP1200_SRAM_SLOWPORT_CONFIG_SRWA_69  0x45000000 /*   R/W      Assert = 69 */
#define   IXP1200_SRAM_SLOWPORT_CONFIG_SCEA_82  0x00520000 /*   Enable   Assert = 82 */
#define   IXP1200_SRAM_SLOWPORT_CONFIG_SCEA_75  0x004B0000 /*   Enable   Assert = 75 */
#define   IXP1200_SRAM_SLOWPORT_CONFIG_SRWD_15  0x00000F00 /*   R/W    Deassert = 15 */
#define   IXP1200_SRAM_SLOWPORT_CONFIG_SRWD_14  0x00000E00 /*   R/W    Deassert = 14 */
#define   IXP1200_SRAM_SLOWPORT_CONFIG_SCED_7   0x00000007 /*   Enable Deassert =  7 */


#define IXP1200_PCI_DRAM_BAR        0x42000018   /* Register Address */
#define IXP1200_PCI_INT_LAT         0x4200003C   /* Register Address */
#define IXP1200_MAILBOX_0           0x42000050   /* Register Address */
#define IXP1200_MAILBOX_1           0x42000054   /* Register Address */
#define IXP1200_MAILBOX_2           0x42000058   /* Register Address */
#define IXP1200_MAILBOX_3           0x4200005C   /* Register Address */
#define IXP1200_DOORBELL            0x42000060   /* Register Address */
#define IXP1200_DOORBELL_SETUP      0x42000064   /* Register Address */
#define IXP1200_RESET               0x4200007C   /* Register Address */
#define RESET_MICROENGINE           0x0000003F   /* Reset 6 microengines */
#define IXP1200_CHAN_1_BYTE_COUNT   0x42000080   /* Register Address */
#define IXP1200_CHAN_2_BYTE_COUNT   0x420000A0   /* Register Address */
#define IXP1200_CHAN_1_PCI_BAR      0x42000084   /* Register Address */
#define IXP1200_CHAN_2_PCI_BAR      0x420000A4   /* Register Address */
#define IXP1200_CHAN_1_DRAM_ADDR    0x42000088   /* Register Address */
#define IXP1200_CHAN_2_DRAM_ADDR    0x420000A8   /* Register Address */
#define IXP1200_CHAN_1_DESC_PTR     0x4200008C   /* Register Address */
#define IXP1200_CHAN_2_DESC_PTR     0x420000AC   /* Register Address */
#define IXP1200_CHAN_1_CONTROL      0x42000090   /* Register Address */
#define IXP1200_CHAN_2_CONTROL      0x420000B0   /* Register Address */
#define   IXP1200_CHAN_CONTROL_CCD    0x00000080 /*   Channel Chain Done */
#define   IXP1200_CHAN_CONTROL_ERR    0x00000008 /*   Channel Error */
#define IXP1200_DMA_INF_MODE        0x4200009C   /* Register Address */
#define IXP1200_CSR_BASE_ADDR_MASK  0x420000F8   /* Register Address */
#define IXP1200_DRAM_BASE_ADDR_MASK 0x42000100   /* Register Address */
#define IXP1200_SA_CONTROL          0x4200013C   /* Register Address */
#define   IXP1200_SA_CONTROL_IC       0x00000001 /*   Initialize Complete */
#define   IXP1200_SA_CONTROL_W1C_MASK 0x00000080 /*   Bits which are W1C  */
#define IXP1200_PCI_ADDR_EXT        0x42000140   /* Register Address */
#define   IXP1200_PCI_ADDR_EXT_PMSA   0x0000E000 /*   PCI Memory Space Addr Bits */
#define IXP1200_DBELL_PCI_MASK      0x42000150   /* Register Address */
#define IXP1200_DBELL_SA_MASK       0x42000154   /* Register Address */

#define IXP1200_IRQ_STATUS          0x42000180   /* Register Address */
#define IXP1200_FIQ_STATUS          0x42000280   /* Register Address */
#define   IXP1200_REQ_STATUS_SI       0x00000002
#define   IXP1200_REQ_STATUS_T1       0x00000010 /*   Timer 1 Status */
#define   IXP1200_REQ_STATUS_T2       0x00000020 /*   Timer 2 Status */
#define   IXP1200_REQ_STATUS_T3       0x00000040 /*   Timer 3 Status */
#define   IXP1200_REQ_STATUS_T4       0x00000080 /*   Timer 4 Status */
#define   IXP1200_REQ_STATUS_DFH      0x00008000
#define   IXP1200_REQ_STATUS_DMA1     0x00010000
#define   IXP1200_REQ_STATUS_DMA2     0x00020000
#define   IXP1200_REQ_STATUS_PIL      0x00040000
#define   IXP1200_REQ_STATUS_DMA1NB   0x00100000
#define   IXP1200_REQ_STATUS_DMA2NB   0x00200000
#define   IXP1200_REQ_STATUS_SB       0x00400000
#define   IXP1200_REQ_STATUS_RESERR   0x00800000
#define   IXP1200_REQ_STATUS_IIP      0x02000000
#define   IXP1200_REQ_STATUS_PWRM     0x04000000
#define   IXP1200_REQ_STATUS_DTE      0x08000000
#define   IXP1200_REQ_STATUS_DPED     0x10000000
#define   IXP1200_REQ_STATUS_RMA      0x20000000
#define   IXP1200_REQ_STATUS_RTA      0x40000000
#define   IXP1200_REQ_STATUS_DPE      0x80000000
#define   IXP1200_REQ_STATUS_ANY      0xFEF780F2

#define IXP1200_IRQ_ENABLE          0x42000188   /* Register Address */
#define IXP1200_FIQ_ENABLE          0x42000288   /* Register Address */
#define IXP1200_IRQ_ENABLE_SET      0x42000188   /* Register Address */
#define IXP1200_FIQ_ENABLE_SET      0x42000288   /* Register Address */
#define IXP1200_IRQ_ENABLE_CLEAR    0x4200018C   /* Register Address */
#define IXP1200_FIQ_ENABLE_CLEAR    0x4200028C   /* Register Address */
#define   IXP1200_REQ_ENABLE_DFH      0x00008000 /*   Doorbell from Host */
#define   IXP1200_REQ_ENABLE_T1       0x00000010 /*   Timer 1 */
#define   IXP1200_REQ_ENABLE_T2       0x00000020 /*   Timer 2 */
#define   IXP1200_REQ_ENABLE_T3       0x00000040 /*   Timer 3 */
#define   IXP1200_REQ_ENABLE_T4       0x00000080 /*   Timer 4 */

#define IXP1200_TIMER_1_LOAD        0x42000300   /* Register Address */
#define IXP1200_TIMER_2_LOAD        0x42000320   /* Register Address */
#define IXP1200_TIMER_3_LOAD        0x42000340   /* Register Address */
#define IXP1200_TIMER_4_LOAD        0x42000360   /* Register Address */
#define IXP1200_TIMER_1_VALUE       0x42000304   /* Register Address */
#define IXP1200_TIMER_2_VALUE       0x42000324   /* Register Address */
#define IXP1200_TIMER_3_VALUE       0x42000344   /* Register Address */
#define IXP1200_TIMER_4_VALUE       0x42000364   /* Register Address */
#define IXP1200_TIMER_1_CONTROL     0x42000308   /* Register Address */
#define IXP1200_TIMER_2_CONTROL     0x42000328   /* Register Address */
#define IXP1200_TIMER_3_CONTROL     0x42000348   /* Register Address */
#define IXP1200_TIMER_4_CONTROL     0x42000368   /* Register Address */
#define   IXP1200_TIMER_CONTROL_d1    0x00000000 /*   divide by   1  */
#define   IXP1200_TIMER_CONTROL_d16   0x00000004 /*   divide by  16  */
#define   IXP1200_TIMER_CONTROL_d256  0x00000008 /*   divide by 256  */
#define   IXP1200_TIMER_CONTROL_per   0x00000040
#define   IXP1200_TIMER_CONTROL_EN        0x00000080
#define IXP1200_TIMER_1_CLEAR       0x4200030C   /* Register Address */
#define IXP1200_TIMER_2_CLEAR       0x4200032C   /* Register Address */
#define IXP1200_TIMER_3_CLEAR       0x4200034C   /* Register Address */
#define IXP1200_TIMER_4_CLEAR       0x4200036C   /* Register Address */


#define IXP1200_PCI_WINDOW_START    0x60000000
#define IXP1200_PCI_WINDOW_LENGTH   0x20000000


#define IXP1200_PLL_CFG             0x90000C00    /* PLL Configuration Register       */
#define   IXP1200_PLL_CFG__29_491     0x00000000  /*   Core =  29.491 MHz             */
#define   IXP1200_PLL_CFG__36_865     0x00000001  /*   Core =  36.865 MHz             */
#define   IXP1200_PLL_CFG__44_237     0x00000002  /*   Core =  44.237 MHz             */
#define   IXP1200_PLL_CFG__51_61      0x00000003  /*   Core =  51.61  MHz             */
#define   IXP1200_PLL_CFG__58_982     0x00000004  /*   Core =  58.982 MHz             */
#define   IXP1200_PLL_CFG__66_355     0x00000005  /*   Core =  66.355 MHz             */
#define   IXP1200_PLL_CFG__73_728     0x00000006  /*   Core =  73.728 MHz             */
#define   IXP1200_PLL_CFG__81_101     0x00000007  /*   Core =  81.101 MHz             */
#define   IXP1200_PLL_CFG__88_474     0x00000008  /*   Core =  88.474 MHz             */
#define   IXP1200_PLL_CFG__95_846     0x00000009  /*   Core =  95.846 MHz             */
#define   IXP1200_PLL_CFG_103_219     0x0000000A  /*   Core = 103.219 MHz             */
#define   IXP1200_PLL_CFG_110_592     0x0000000B  /*   Core = 110.592 MHz             */
#define   IXP1200_PLL_CFG_132_71      0x0000000C  /*   Core = 132.71  MHz             */
#define   IXP1200_PLL_CFG_147_456     0x0000000D  /*   Core = 147.456 MHz             */
#define   IXP1200_PLL_CFG_154_829     0x0000000E  /*   Core = 154.829 MHz             */
#define   IXP1200_PLL_CFG_162_202     0x0000000F  /*   Core = 162.202 MHz             */
#define   IXP1200_PLL_CFG_165_89      0x00000010  /*   Core = 165.89  MHz             */
#define   IXP1200_PLL_CFG_176_947     0x00000011  /*   Core = 176.947 MHz             */
#define   IXP1200_PLL_CFG_191_693     0x00000012  /*   Core = 191.693 MHz             */
#define   IXP1200_PLL_CFG_199_066     0x00000013  /*   Core = 199.066 MHz             */

#define IXP1200_FIQ                 0x90001000
#define IXP1200_IRQ                 0x90001400
#define   IXP1200_REQ_PCI             0x00000004
#define   IXP1200_REQ_CINT            0x00000008
#define   IXP1200_REQ_UENG            0x00000010
#define   IXP1200_REQ_SRAM            0x00000020
#define   IXP1200_REQ_RTC             0x00000040
#define   IXP1200_REQ_SDRAM           0x00000080
#define   IXP1200_REQ_UART            0x00000100
#define   IXP1200_REQ_MBZ             0x80000000
#define   IXP1200_REQ_ANY             0x000001FC

#define IXP1200_GPIO_EN             0x90001800    /* Register Address */
#define   IXP1200_GPIO_EN_CCCC_IIII   0x00000000  /*   Core owns all GPIO; All input */

#define IXP1200_GPIO_DATA           0x90001C00    /* Register Address */

#define IXP1200_RTC_DIV             0x90002000
#define IXP1200_RTC_TINT            0x90002400
#define IXP1200_RTC_TVAL            0x90002800
#define IXP1200_RTC_CNTR            0x90002C00
#define IXP1200_RTC_ALM             0x90003000

#define IXP1200_UART_SR             0x90003400    /* UART Status Register Address     */
#define   IXP1200_UART_SR_TXF         0x00000080  /*   Transmit FIFO full bit         */
#define   IXP1200_UART_SR_TXE         0x00000020  /*   Transmit FIFO empty bit        */
#define   IXP1200_UART_SR_RXR         0x00000010  /*   Receive FIFO ready (not empty) */
#define   IXP1200_UART_SR_TXR         0x00000002  /*   Transmit Fifo Ready (not full) */

#define IXP1200_UART_CR             0x90003800    /* UART Control Register Address    */
#define   IXP1200_UART_CR_BRD_9600    0x00170000  /*   Baud Rate Divisor =   9600     */
#define   IXP1200_UART_CR_BRK         0x00000001  /*   Transmit Break.                */
#define   IXP1200_UART_CR_PE          0x00000002  /*   Parity Enable.                 */
#define   IXP1200_UART_CR_PS          0x00000004  /*   Parity Odd (Even)              */
#define   IXP1200_UART_CR_SBS         0x00000008  /*   Stop Bit Select 2 (1) bits     */
#define   IXP1200_UART_CR_SBS_1       0x00000000  /*   Stop Bit Select = 1 stop bit   */
#define   IXP1200_UART_CR_SBS_2       0x00000008  /*   Stop Bit Select = 2 stop bit   */
#define   IXP1200_UART_CR_RIE         0x00000010  /*   Receive interrupt enable       */
#define   IXP1200_UART_CR_DSS_5       0x00000000  /*   Data Size Select = 5 bits      */
#define   IXP1200_UART_CR_DSS_6       0x00000020  /*   Data Size Select = 6 bits      */
#define   IXP1200_UART_CR_DSS_7       0x00000040  /*   Data Size Select = 7 bits      */
#define   IXP1200_UART_CR_DSS_8       0x00000060  /*   Data Size Select = 8 bits      */
#define   IXP1200_UART_CR_UE          0x00000080  /*   UART Enable                    */
#define   IXP1200_UART_CR_XIE         0x00000100  /*   Transmit interrupt enable      */
#define   IXP1200_UART_CR_UIS         0x00000200  /*   Interrupt Select FIQ (IRQ)     */

#define IXP1200_UART_DR             0x90003C00    /* UART Data Register Address       */


#define IXP1200_THREAD_DONE_REG0    0xB0040008
#define IXP1200_THREAD_DONE_REG1    0xB004000C
#define IXP1200_RCV_CNTL            0xB0040018
#define IXP1200_RCV_REQ             0xB004001C
#define IXP1200_SOP_SEQ1            0xB0040020 /* Fast Port 1 Sequence # */
#define IXP1200_SOP_SEQ2            0xB0040024 /* Fast Port 2 Sequence # */
#define IXP1200_ENQUEUE_SEQ1        0xB0040028 /* Enqueue Sequence # 1 */
#define IXP1200_ENQUEUE_SEQ2        0xB004002C /* Enqueue Sequence # 1 */
#define IXP1200_REC_FASTPORT_CTL    0xB0040030
#define IXP1200_RCV_RDY_CNT         0xB00400C0
#define IXP1200_RCV_RDY_LO          0xB00400C4
#define IXP1200_RCV_RDY_HI          0xB00400C8
#define IXP1200_XMIT_PTR            0xB00400E0
#define IXP1200_XMIT_RDY_LO         0xB00400E4
#define IXP1200_XMIT_RDY_HI         0xB00400E8
#define IXP1200_RCV_RDY_CTL         0xB00400F8
#define IXP1200_XMIT_RDY_CTL        0xB00400FC
#define IXP1200_HASH_MULTIPLIER_64_LO      0xB0040140
#define IXP1200_HASH_MULTIPLIER_64_HI      0xB0040144
#define IXP1200_HASH_MULTIPLIER_48_LO      0xB0040148
#define IXP1200_HASH_MULTIPLIER_48_HI      0xB004014C
#define IXP1200_RDYBUS_TEMPLATE_CTL        0xB0040180
#define IXP1200_RDYBUS_SYNCH_COUNT_DEFAULT 0xB0040190
#define IXP1200_FLOWCTL_MASK        0xB0040194
#define IXP1200_SEND_CMD            0xB0040198
#define IXP1200_FP_READY_WAIT       0xB00401A4
#define IXP1200_GET_CMD             0xB00401B0
#define IXP1200_INTER_THD_SIG       0xB00401C0
#define IXP1200_SELF_DESTRUCT       0xB00401D4
#define IXP1200_IREG                0xB00401E0    /* Interrupt Register               */


#define IXP1200_SCRATCH_PAD_MEMORY  0xB0044000
#define IXP1200_SCRATCH_START       0xB0044000
#define IXP1200_SCRATCH_LENGTH      0x00001000


#define IXP1200_SDRAM_CSR                0xFF000000    /* SDRAM CSR Address */
#define   IXP1200_SDRAM_CSR_INIT           0x00000001  /*   Initialize SDRAM Unit */

#define IXP1200_SDRAM_MEMCTL0            0xFF000004    /* SDRAM timing settings  */
#define   IXP1200_SDRAM_MEMCTL0_RFRSH__229 0x00E50000  /*   Refresh Count =  229 */
#define   IXP1200_SDRAM_MEMCTL0_RFRSH__805 0x03250000  /*   Refresh Count =  805 */
#define   IXP1200_SDRAM_MEMCTL0_RFRSH_1295 0x050F0000  /*   Refresh Count = 1295 */
#define   IXP1200_SDRAM_MEMCTL0_RFRSH_1381 0x05650000  /*   Refresh Count = 1381 */
#define   IXP1200_SDRAM_MEMCTL0_RFRSH_1554 0x06120000  /*   Refresh Count = 1554 */
#define   IXP1200_SDRAM_MEMCTL0_BURSTL_8   0x00008000  /*   Burst Length = 8     */
#define   IXP1200_SDRAM_MEMCTL0_CASL_2     0x00000200  /*   CAS Latency = 2      */
#define   IXP1200_SDRAM_MEMCTL0_RAW_12     0x000000C0  /*   Row Addr Width = 12  */
#define   IXP1200_SDRAM_MEMCTL0_CAW_8      0x00000008  /*   Col Addr Width = 8   */

#define IXP1200_SDRAM_MEMCTL1            0xFF000008    /* SDRAM timing settings   */
#define   IXP1200_SDRAM_MEMCTL1_TRWT_1     0x10000000  /*   Read/Write turnaround = 1 */
#define   IXP1200_SDRAM_MEMCTL1_TDPL_2     0x02000000  /*   Data In to Precharge  = 2 */
#define   IXP1200_SDRAM_MEMCTL1_TDQZ_3     0x00300000  /*   DQM Data Out Disable  = 3 */
#define   IXP1200_SDRAM_MEMCTL1_TRC_6      0x00060000  /*   Bank Cycle            = 6 */
#define   IXP1200_SDRAM_MEMCTL1_TRRD_1     0x00001000  /*   Bank to Bank delay    = 1 */
#define   IXP1200_SDRAM_MEMCTL1_TRCD_1     0x00000100  /*   RAS to CAS delay      = 1 */
#define   IXP1200_SDRAM_MEMCTL1_TRASMIN_4  0x00000040  /*   Active Command Period = 4 */
#define   IXP1200_SDRAM_MEMCTL1_TRP_1      0x00000001  /*   Precharge Time        = 1 */

#define IXP1200_SDRAM_MEMINIT            0xFF00000C    /* SDRAM initialization       */
#define   IXP1200_SDRAM_MEMINIT_TRSC_1     0x00100000  /*   tRSC = 1 cycles          */
#define   IXP1200_SDRAM_MEMINIT_IR_2       0x00020000  /*   2 Initial Refresh cycles */
#define   IXP1200_SDRAM_MEMINIT_ID_1475    0x000005C3  /*   Initial Delay = 1475 cyc */
#define   IXP1200_SDRAM_MEMINIT_ID_5161    0x00001429  /*   Initial Delay = 5161 cyc */
#define   IXP1200_SDRAM_MEMINIT_ID_8295    0x00002067  /*   Initial Delay = 8295 cyc */
#define   IXP1200_SDRAM_MEMINIT_ID_8848    0x00002290  /*   Initial Delay = 8848 cyc */
#define   IXP1200_SDRAM_MEMINIT_ID_9954    0x000026E2  /*   Initial Delay = 9954 cyc */


#define CSR_BAM_128B      0x00000000     /* Not supported by Intel */
#define CSR_BAM_512K      0x00040000
#define CSR_BAM_1M        0x000C0000
#define CSR_BAM_2M        0x001C0000
#define CSR_BAM_4M        0x003C0000
#define CSR_BAM_8M        0x007C0000
#define CSR_BAM_16M       0x00FC0000
#define CSR_BAM_32M       0x01FC0000
#define CSR_BAM_64M       0x03FC0000
#define CSR_BAM_128M      0x07FC0000
#define CSR_BAM_256M      0x0FFC0000

#define DRAM_BAM_0B       0x8FFC0000
#define DRAM_BAM_256K     0x00000000
#define DRAM_BAM_512K     0x00040000
#define DRAM_BAM_1M       0x000C0000
#define DRAM_BAM_2M       0x001C0000
#define DRAM_BAM_4M       0x003C0000
#define DRAM_BAM_8M       0x007C0000
#define DRAM_BAM_16M      0x00FC0000
#define DRAM_BAM_32M      0x01FC0000
#define DRAM_BAM_64M      0x03FC0000
#define DRAM_BAM_128M     0x07FC0000
#define DRAM_BAM_256M     0x0FFC0000

#define IXP1200_SMALL_PAGE_SIZE   4096
#define IXP1200_SECTION_SIZE   (1024*1024)

#endif
